Certain memory subsystems include register devices connected to the address or command bus of the memory subsystem to store values related to a command or a configuration within the memory subsystem. Traditionally there is no good way to access such data. Thus, data stored in the register for purposes of configuration (e.g., data stored in a Mode Register) or data stored for debug or error detection purposes (e.g., data stored in a C/A register device) or other data in another such register is not easily accessible.
One option to access the data is to include a connection to the data bus of the memory subsystem. Such an option is very expensive in terms of hardware (extra pins) and routing of traces. Another option is to put the device in a special state (e.g., a management mode) to temporarily allow repurposing of the existing buses or other connections. Such an option results in a slow connection, and does not allow continued operation of the device, and may still require additional hardware. Another option is to provide an out-of-band serial interface on the register device, which also adds hardware and routing costs. Thus, there are currently no traditional mechanisms that allow access to the data stored in registers of the memory subsystem with standard commands with minimal hardware requirements.
Memory subsystems that support newer standards of DDR (dual data rate) memory add an additional circumstance of providing a register and logic for performing parity error checking at the register device instead of at the memory device. For example, DDR4 (standard still in development as of the filing of this application) will allow command/address (C/A) parity error checking off the DRAM (dynamic random access memory) device. However, without a mechanism to read a parity error, the command will still be send to the DRAM for execution, which would result in hanging the computing device (for example, a “blue screen” condition).
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.